/**
 @file sys_tmg_serdes.h

 @author  Copyright (C) 2023 Centec Networks Inc.  All rights reserved.

 @date 2023-02-10

 @version v1.0

*/

#ifndef _SYS_TMG_SERDES_H
#define _SYS_TMG_SERDES_H
#ifdef __cplusplus
extern "C" {
#endif

/***************************************************************
 *
 * Header Files
 *
 ***************************************************************/
#include "sys_tmg_datapath.h"

/***************************************************************
 *
 * Defines and Macros
 *
 ***************************************************************/

typedef struct sys_tmg_serdes_temp_soft_table_s
{
    uint8  enable;
    uint8  serdes_speed;

}sys_tmg_serdes_temp_soft_table_t;

/*cr interface*/

/*FIELD_DEFINE*/
#define TMG_SERDES_FLD_DEF(type, offset, hi_bit, lo_bit) { \
    type,   \
    offset, \
    hi_bit, \
    lo_bit, \
    (hi_bit-lo_bit) + 1, \
    (uint16) ((((uint64) 1 << ((hi_bit-lo_bit) + 1)) - 1) << lo_bit), \
    (uint16) ~((((uint64) 1 << ((hi_bit-lo_bit) + 1)) - 1) << lo_bit)}

/*EXTRACT_FIELD*/
#define TMG_SERDES_FLD(xFIELD) { \
    xFIELD.type, \
    xFIELD.offset, \
    xFIELD.hi_bit, \
    xFIELD.lo_bit, \
    xFIELD.total_bits, \
    xFIELD.mask, \
    xFIELD.retain_mask}

struct _sys_tmg_serdes_field_s
{
    uint16 type;
    uint16 offset;
    int16  hi_bit;
    int16  lo_bit;
    int16  total_bits;
    uint16 mask;
    uint16 retain_mask;
};
typedef struct _sys_tmg_serdes_field_s _sys_tmg_serdes_field_t;

enum sys_tmg_serdes_reg_type_e
{
    PMA_SUP_AND_RAW_CMN = 0,
    PMA_LANE            = 1,
    RAW_LANE            = 2,
    RAW_AON_LANE        = 3,
    ANLT_TOP            = 4,
    AN_LANE             = 0x410,
    LT_CTRL             = 0x450,
    LT_STS              = 0x458
};

#define REG_STR(FLD_DEF) (&(_sys_tmg_serdes_field_t)FLD_DEF)

#define TMG_SERDES_ADDRESS_TYPE_SHIFT       12
#define TMG_SERDES_ADDRESS_LANE_SHIFT       9
#define TMG_SERDES_ADDRESS_ANLT_TYPE_SHIFT  4
#define TMG_SERDES_ADDRESS_ANLT_LANE_SHIFT  8

#define TMG_SERDES_GET_ADDRESS(type, serdes_id, offset, address) \
    do\
    {\
        uint8 lane_id;\
        lane_id =  SYS_TMG_GET_INNER_LANE_BY_SERDES(serdes_id);\
        if(PMA_SUP_AND_RAW_CMN == type || ANLT_TOP == type)\
        {\
            address = type << TMG_SERDES_ADDRESS_TYPE_SHIFT | offset;\
        }\
        else if(AN_LANE == type || LT_CTRL == type || LT_STS == type)\
        {\
            address = (type << TMG_SERDES_ADDRESS_ANLT_TYPE_SHIFT) + (lane_id << TMG_SERDES_ADDRESS_ANLT_LANE_SHIFT) + offset;\
        }\
        else \
        {\
            address = (type << TMG_SERDES_ADDRESS_TYPE_SHIFT) | (((lane_id * 2) << TMG_SERDES_ADDRESS_ANLT_LANE_SHIFT) + offset);\
        }\
    }\
    while(0)\

/* internal register define  */
#define TMG_SERDES_FW_VERSION_A                 TMG_SERDES_FLD_DEF(PMA_SUP_AND_RAW_CMN, 0x178, 15, 12)
#define TMG_SERDES_FW_VERSION_B                 TMG_SERDES_FLD_DEF(PMA_SUP_AND_RAW_CMN, 0x178, 11, 4)
#define TMG_SERDES_FW_VERSION_C                 TMG_SERDES_FLD_DEF(PMA_SUP_AND_RAW_CMN, 0x178, 3 , 0)
#define TMG_SERDES_FW_MEM_ADDR_MON              TMG_SERDES_FLD_DEF(RAW_LANE, 0x65, 15, 0) 


#define TMG_SERDES_EQ_CTLE_BOOST_ASIC           TMG_SERDES_FLD_DEF(PMA_LANE, 0x12, 13, 9)
#define TMG_SERDES_EQ_CTLE_POLE_ASIC            TMG_SERDES_FLD_DEF(PMA_LANE, 0x13, 1, 0) 

#define TMG_SERDES_TX_PRBS_MODE                 TMG_SERDES_FLD_DEF(PMA_LANE, 0x71, 3, 0)
#define TMG_SERDES_RX_PRBS_MODE                 TMG_SERDES_FLD_DEF(PMA_LANE, 0x93, 3, 0)
#define TMG_SERDES_PRBS_OV14                    TMG_SERDES_FLD_DEF(PMA_LANE, 0x94, 15, 15)
#define TMG_SERDES_PRBS_COUNT                   TMG_SERDES_FLD_DEF(PMA_LANE, 0x94, 14, 0)
#define TMG_SERDES_PRBS_SYNC                    TMG_SERDES_FLD_DEF(PMA_LANE, 0x93, 4, 4)
#define TMG_SERDES_PRBS_TRIGGER_ERR             TMG_SERDES_FLD_DEF(PMA_LANE, 0x71, 4, 4)

#define TMG_SERDES_TX_DATA_EN_LOW               TMG_SERDES_FLD_DEF(PMA_LANE, 0x0d, 3, 3)
#define TMG_SERDES_RX_DATA_EN                   TMG_SERDES_FLD_DEF(PMA_LANE, 0x31, 2, 2)

#define TMG_SERDES_MPLLA_CONT_LOCK_DET_EN       TMG_SERDES_FLD_DEF(PMA_SUP_AND_RAW_CMN, 0xa2, 14, 14)    
#define TMG_SERDES_MPLLA_VCO_DRIFT              TMG_SERDES_FLD_DEF(PMA_SUP_AND_RAW_CMN, 0xa8, 13, 13)

#define TMG_SERDES_ROPLL_PH_LOCK                TMG_SERDES_FLD_DEF(PMA_LANE, 0x69, 15, 15)

/*AN Related Start*/
#define TMG_SERDES_AN_ADV3                      TMG_SERDES_FLD_DEF(AN_LANE, 0x12, 15, 0)
#define TMG_SERDES_AN_ADV2                      TMG_SERDES_FLD_DEF(AN_LANE, 0x11, 15, 0)
#define TMG_SERDES_AN_ADV1                      TMG_SERDES_FLD_DEF(AN_LANE, 0x10, 15, 0)
#define TMG_SERDES_LP_AN_ABL3                   TMG_SERDES_FLD_DEF(AN_LANE, 0x15, 15, 0)
#define TMG_SERDES_LP_AN_ABL2                   TMG_SERDES_FLD_DEF(AN_LANE, 0x14, 15, 0)
#define TMG_SERDES_LP_AN_ABL1                   TMG_SERDES_FLD_DEF(AN_LANE, 0x13, 15, 0)

#define TMG_SERDES_AN_AUTO_NP_EN                TMG_SERDES_FLD_DEF(AN_LANE, 0xc0, 3, 3)
#define TMG_SREDES_AN_CTRL_EXT_NP_CTL           TMG_SERDES_FLD_DEF(AN_LANE, 0x0, 13, 13)

#define TMG_SERDES_XNP_TX3                      TMG_SERDES_FLD_DEF(AN_LANE, 0x18, 15, 0)
#define TMG_SERDES_XNP_TX2                      TMG_SERDES_FLD_DEF(AN_LANE, 0x17, 15, 0)
#define TMG_SERDES_XNP_TX1                      TMG_SERDES_FLD_DEF(AN_LANE, 0x16, 15, 0)
#define TMG_SERDES_LP_XNP_ABL3                  TMG_SERDES_FLD_DEF(AN_LANE, 0x1b, 15, 0)
#define TMG_SERDES_LP_XNP_ABL2                  TMG_SERDES_FLD_DEF(AN_LANE, 0x1a, 15, 0)
#define TMG_SERDES_LP_XNP_ABL1                  TMG_SERDES_FLD_DEF(AN_LANE, 0x19, 15, 0)

#define TMG_SERDES_VR_UF_XNP_TX3                TMG_SERDES_FLD_DEF(AN_LANE, 0xce, 15, 0)
#define TMG_SERDES_VR_UF_XNP_TX2                TMG_SERDES_FLD_DEF(AN_LANE, 0xcd, 15, 0)
#define TMG_SERDES_VR_UF_XNP_TX1                TMG_SERDES_FLD_DEF(AN_LANE, 0xcc, 15, 0)
#define TMG_SERDES_VR_LP_UF_XNP_ABL3            TMG_SERDES_FLD_DEF(AN_LANE, 0xd1, 15, 0)
#define TMG_SERDES_VR_LP_UF_XNP_ABL2            TMG_SERDES_FLD_DEF(AN_LANE, 0xd0, 15, 0)
#define TMG_SERDES_VR_LP_UF_XNP_ABL1            TMG_SERDES_FLD_DEF(AN_LANE, 0xcf, 15, 0)

#define TMG_SERDES_AN_EXT_NP_STS                TMG_SERDES_FLD_DEF(AN_LANE, 0x01, 7, 7)
#define TMG_SERDES_AN_STS_PAGE_RCVD             TMG_SERDES_FLD_DEF(AN_LANE, 0x01, 6, 6)
#define TMG_SERDES_AN_STS_AN_COMPLETE           TMG_SERDES_FLD_DEF(AN_LANE, 0x01, 5, 5)
#define TMG_SERDES_AN_STS_AN_REMOTE_FAULT       TMG_SERDES_FLD_DEF(AN_LANE, 0x01, 4, 4)
#define TMG_SERDES_AN_STS_AN_ABILITY            TMG_SERDES_FLD_DEF(AN_LANE, 0x01, 3, 3)
#define TMG_SERDES_AN_STS_AM_LINK_STS           TMG_SERDES_FLD_DEF(AN_LANE, 0x01, 2, 2)
#define TMG_SERDES_AN_STS_LP_AN_ABILITY         TMG_SERDES_FLD_DEF(AN_LANE, 0x01, 0, 0)

#define TMG_SERDES_AN_INT_CNT_AN_INC_CNT               TMG_SERDES_FLD_DEF(AN_LANE, 0xA3, 15, 8)
#define TMG_SERDES_AN_INT_CNT_AN_COMPLETE              TMG_SERDES_FLD_DEF(AN_LANE, 0xA3, 7,  0)
#define TMG_SERDES_AN_INT_CNT_LNK_FAIL_INHBT_DONE      TMG_SERDES_FLD_DEF(AN_LANE, 0xa4, 15, 8)
#define TMG_SERDES_AN_INT_CNT_AN_PG_RCV                TMG_SERDES_FLD_DEF(AN_LANE, 0xa4, 7,  0)
#define TMG_SERDES_AN_INT_CNT_LINK_STATUS_FAIL         TMG_SERDES_FLD_DEF(AN_LANE, 0xa5, 15, 8)
#define TMG_SERDES_AN_INT_CNT_AN_RECEIVE_IDLE          TMG_SERDES_FLD_DEF(AN_LANE, 0xa5, 7,  0)
#define TMG_SERDES_AN_INT_CNT_AN_GOOD_CHECK            TMG_SERDES_FLD_DEF(AN_LANE, 0xa6, 15, 8)
#define TMG_SERDES_AN_INT_CNT_PARA_DET_FAULT           TMG_SERDES_FLD_DEF(AN_LANE, 0xa6, 7,  0)

#define TMG_SERDES_AN_INT_ENABLE_AN_GOOD_CHECK         TMG_SERDES_FLD_DEF(AN_LANE, 0xa1, 7,  7)
#define TMG_SERDES_AN_INT_ENABLE_AN_INC_LINK           TMG_SERDES_FLD_DEF(AN_LANE, 0xa1, 1,  1)

#define TMG_SERDES_VR_AN_MODE_CTRL_RX_POL_INV           TMG_SERDES_FLD_DEF(AN_LANE, 0xc0, 11,  11)
#define TMG_SERDES_VR_AN_MODE_CTRL_TX_POL_INV           TMG_SERDES_FLD_DEF(AN_LANE, 0xc0, 10,  10)
#define TMG_SERDES_VR_AN_MODE_CTRL_ACK2_DET_EN          TMG_SERDES_FLD_DEF(AN_LANE, 0xc0, 4,   4)

#define TMG_SERDES_ANLT_TOP_AN_INT_ENABLE               TMG_SERDES_FLD_DEF(ANLT_TOP, 0x1,  11, 8)
#define TMG_SERDES_ANLT_TOP_LT_INT_ENABLE               TMG_SERDES_FLD_DEF(ANLT_TOP, 0x1,  7,  4)

#define TMG_SERDES_AN_ENABLE                    TMG_SERDES_FLD_DEF(AN_LANE, 0, 12, 12)
#define TMG_SERDES_AN_RESTART                   TMG_SERDES_FLD_DEF(AN_LANE, 0, 9, 9)
#define TMG_SERDES_LT_ENABLE                    TMG_SERDES_FLD_DEF(LT_CTRL, 0x10, 0, 0)

#define TMG_SERDES_RX_DFE_BYPASS                    TMG_SERDES_FLD_DEF(PMA_LANE, 0x31, 13, 13)
#define TMG_SERDES_VR_AN_LINK_FAIL_INHIBIT_TIMER_EN TMG_SERDES_FLD_DEF(AN_LANE, 0xd8, 0, 0)
#define TMG_SERDES_VR_AN_WAIT_TIMER                 TMG_SERDES_FLD_DEF(AN_LANE, 0xc2, 15, 0)
#define TMG_SERDES_VR_AN_BREAK_TIMER                TMG_SERDES_FLD_DEF(AN_LANE, 0xc3, 15, 0)

#define TMG_SERDES_AN_INT_STATUS_GOOD_CHECK         TMG_SERDES_FLD_DEF(AN_LANE, 0xa0, 7, 7)
#define TMG_SERDES_AN_INT_STATUS_AN_INC_LINK        TMG_SERDES_FLD_DEF(AN_LANE, 0xa0, 1, 1)
#define TMG_SERDES_VR_AN_FSM_HOLD_INCOMPATIBLE_LINK TMG_SERDES_FLD_DEF(AN_LANE, 0xc1, 1, 1)
#define TMG_SERDES_AN_TOP_INT_STATUS                TMG_SERDES_FLD_DEF(ANLT_TOP, 0x0,  7, 4)

/*AN Related End*/
/*Lt Related Start*/
#define TMG_SERDES_VR_AN_MODE_CTRL_PCS_TYPE_SEL     TMG_SERDES_FLD_DEF(AN_LANE, 0xc0, 15, 12)
#define TMG_SERDES_LT_CL72_SEL                      TMG_SERDES_FLD_DEF(LT_CTRL, 0x13, 0, 0)
#define TMG_SERDES_LT_START_EN_AFTR_AN              TMG_SERDES_FLD_DEF(LT_CTRL, 0x12, 0, 0)
#define TMG_SERDES_LT_MAX_WAIT_TIMEL                TMG_SERDES_FLD_DEF(LT_CTRL, 0x20, 15, 0)
#define TMG_SERDES_LT_MAX_WAIT_TIMEH                TMG_SERDES_FLD_DEF(LT_CTRL, 0x21, 15, 0)
#define TMG_SERDES_LT_LINKRDY_WAIT_TIME             TMG_SERDES_FLD_DEF(LT_CTRL, 0x22, 15, 0)
#define TMG_SERDES_LT_RX_TRAIN_TIME_L               TMG_SERDES_FLD_DEF(LT_CTRL, 0x23, 15, 0)
#define TMG_SERDES_LT_RX_TRAIN_TIME_H               TMG_SERDES_FLD_DEF(LT_CTRL, 0x24, 15, 0)
#define TMG_SERDES_LT_RX_EQ_SEQ_PAR_SEL             TMG_SERDES_FLD_DEF(LT_CTRL, 0x42, 0,  0)
#define TMG_SERDES_LT_LINKRDY_WAIT_TIME             TMG_SERDES_FLD_DEF(LT_CTRL, 0x22, 15, 0)
#define TMG_SERDES_LT_RESTART                       TMG_SERDES_FLD_DEF(LT_CTRL, 0x11, 0,  0)
#define TMG_SERDES_LT_INT_STATUS_LT_TRAIN_OVER      TMG_SERDES_FLD_DEF(LT_CTRL,  0x0,  0, 0)
#define TMG_SERDES_LT_INT_STATUS_LT_TRAIN_FAIL      TMG_SERDES_FLD_DEF(LT_CTRL,  0x0,  1, 1)
#define TMG_SERDES_LT_INT_TRAIN_OK                  TMG_SERDES_FLD_DEF(LT_STS,   0x10, 4, 4)
#define TMG_SERDES_LT_INT_ENABLE_LT_TRAIN_OVER      TMG_SERDES_FLD_DEF(LT_CTRL,  0x1,  0, 0)
#define TMG_SERDES_LT_INT_ENABLE_LT_TRAIN_FAIL      TMG_SERDES_FLD_DEF(LT_CTRL,  0x1,  1, 1)
#define TMG_SERDES_LT_STS_LT_SIGNAL_DETECT          TMG_SERDES_FLD_DEF(LT_STS,   0x10, 4, 4)
#define TMG_SERDES_LT_TOP_INT_STATUS                TMG_SERDES_FLD_DEF(ANLT_TOP, 0x0, 11, 8)
#define TMG_SERDES_LT_SOFT_RST                      TMG_SERDES_FLD_DEF(ANLT_TOP, 0x3, 15, 12)
#define TMG_SERDES_LT_RXADAPT_IN_PROG_TIME          TMG_SERDES_FLD_DEF(LT_CTRL, 0x25, 15, 0)
#define TMG_SERDES_LT_CTRL_FSM_STATE_HIS            TMG_SERDES_FLD_DEF(LT_CTRL, 0x12, 15, 0)
/*Lt Related End*/

/*Signal quality related Start*/
#define TMG_SERDES_RX_VALID_COARSE_ADAPT            TMG_SERDES_FLD_DEF(RAW_LANE, 0x31, 0, 0)        

/*Signal quality related End*/


/*Rx Adapt related Start*/
#define TMG_SREDES_ADAPT_CONT_STATUS                TMG_SERDES_FLD_DEF(RAW_LANE, 0x103, 0, 0)
#define TMG_SERDES_LT_RX_ADAPT_REQ                  TMG_SERDES_FLD_DEF(LT_CTRL,  0x71 , 0, 0)
#define TMG_SERDES_RX_CDR_DETECTOR_EN               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x67, 0, 0)
#define TMG_SREDES_SIGDET_HF_EN_OVRD_EN             TMG_SERDES_FLD_DEF(PMA_LANE, 0x28, 11, 11)
#define TMG_SREDES_SIGDET_HF_EN_OVRD_VAL            TMG_SERDES_FLD_DEF(PMA_LANE, 0x28, 10, 10)

#define TMG_SREDES_RX_ADAPT_CFG_CTLE_EN             TMG_SERDES_FLD_DEF(PMA_LANE, 0xa8, 7, 0)


/*dfe has 1-9 fixed tap and 9-20 float tap*/
#define TMG_SERDES_DFE_TAP1_ADPT_VAL                TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x18, 13, 0)    
#define TMG_SERDES_DFE_TAP2_ADPT_VAL                TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x19, 12, 0)  
#define TMG_SERDES_DFE_TAP3_ADPT_VAL                TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x1a, 11, 0)  
#define TMG_SERDES_DFE_TAP4_ADPT_VAL                TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x1b, 11, 0)    
#define TMG_SERDES_DFE_TAP5_ADPT_VAL                TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x1c, 11, 0)  
#define TMG_SERDES_DFE_TAP6_ADPT_VAL                TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0xa8, 11, 0)  
#define TMG_SERDES_DFE_TAP7_ADPT_VAL                TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0xa9, 11, 0)    
#define TMG_SERDES_DFE_TAP8_ADPT_VAL                TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0xaa, 11, 0)  
#define TMG_SERDES_DFE_TAP9_ADPT_VAL                TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x1a, 11, 0)  
#define TMG_SERDES_DFE_FTAP0_CORR_MAG               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x120, 15, 0)    
#define TMG_SERDES_DFE_FTAP1_CORR_MAG               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x121, 15, 0)
#define TMG_SERDES_DFE_FTAP2_CORR_MAG               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x122, 15, 0)
#define TMG_SERDES_DFE_FTAP3_CORR_MAG               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x123, 15, 0)    
#define TMG_SERDES_DFE_FTAP4_CORR_MAG               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x124, 15, 0)
#define TMG_SERDES_DFE_FTAP5_CORR_MAG               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x125, 15, 0)
#define TMG_SERDES_DFE_FTAP6_CORR_MAG               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x126, 15, 0)    
#define TMG_SERDES_DFE_FTAP7_CORR_MAG               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x127, 15, 0)
#define TMG_SERDES_DFE_FTAP8_CORR_MAG               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x128, 15, 0)
#define TMG_SERDES_DFE_FTAP9_CORR_MAG               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x129, 15, 0)    
#define TMG_SERDES_DFE_FTAP10_CORR_MAG              TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x12a, 15, 0)
#define TMG_SERDES_DFE_FTAP11_CORR_MAG              TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x12b, 15, 0)

#define TMG_SERDES_DFE_FTAP_SORT_ACK                TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x12d, 0, 0)
#define TMG_SERDES_DFE_FTAP_SORT_REQ                TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x12c, 0, 0)

#define TMG_SERDES_DFE_FTAP_SORT0_POS               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x12e, 15, 12)
#define TMG_SERDES_DFE_FTAP_SORT1_POS               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x12e, 11, 8)
#define TMG_SERDES_DFE_FTAP_SORT2_POS               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x12e, 7,  4)
#define TMG_SERDES_DFE_FTAP_SORT3_POS               TMG_SERDES_FLD_DEF(RAW_AON_LANE, 0x12e, 3, 0)



/*Rx Adapt related End*/


enum sys_tmg_serdes_loopback_mode_e
{
    TMG_SERDES_LOOPBACK_TX2RX = 0,
    TMG_SERDES_LOOPBACK_RX2TX = 1    
};

enum sys_tmg_global_refclk_sel_e
{
    TMG_SERDES_REF_ALT0_CLK = 0,
    TMG_SERDES_REF_PAD_CLK  = 1,
    TMG_SERDES_REF_ALT1_CLK = 2,
    TMG_SERDES_REF_SEL_TOTALCNT
};

enum sys_tmg_serdes_pll_e
{
    TMG_SERDES_PLLA = 0,
    TMG_SERDES_PLLB = 1   
};

enum sys_tmg_serdes_ref_e
{
    TMG_SERDES_REFA = 0,
    TMG_SERDES_REFB = 1,
    TMG_SERDES_REF_TOTALCNT 
};

enum sys_tmg_serdes_tx_pstate_e
{
    TMG_SERDES_TX_P0_STATE     = 0,    /* fully powerup */
    TMG_SERDES_TX_P0S_STATE    = 1,    /*Transmitter common mode is held, TX analog clocks are active, but TX serializer is off.*/
    TMG_SERDES_TX_P1_STATE     = 2,    /*Transmitter common mode is held, but TX analog clocks and TX serializer are off.*/
    TMG_SERDES_TX_P2_STATE     = 3     /*Transmitter is powered down.*/
};

enum sys_tmg_serdes_rx_pstate_e
{
    TMG_SERDES_RX_P0_STATE     = 0,    /* fully powerup */
    TMG_SERDES_RX_P0S_STATE    = 1,    /*RX voltage-controlled oscillator (VCO) is in continuous calibration mode, output receive clocks are not available*/
    TMG_SERDES_RX_P1_STATE     = 2,    /*RX analog front-end (AFE) and voltage regulators are powered up, but RX VCO is in reset*/
    TMG_SERDES_RX_P2_STATE     = 3     /*RX signal detector is powered up and the rest of RX is powered down*/
};

enum sys_tmg_serdes_pll_config_list_item_e
{
    Hss32GPll_cfgRefRange,
    Hss32GPll_cfgRefRawClkDiv2En,
    Hss32GPll_cfgPllClkDiv4En,
    Hss32GPll_cfgPllMulti,
    Hss32GPll_cfgPllTxClkDiv,
    Hss32GPll_cfgPllWordClkDiv,
    Hss32GPll_cfgPllSscEn,
    Hss32GPll_cfgPllSscUpSpread,
    Hss32GPll_cfgPllSscPeak,
    Hss32GPll_cfgPllSscStepSize,
    Hss32GPll_cfgPllFracEn,
    Hss32GPll_cfgPllFracQuot,
    Hss32GPll_cfgPllFracDen,
    Hss32GPll_cfgPllFracRem,
    Hss32GPll_cfgRefLaneClkEn,
    Hss32GPll_cfgPllCalDis,
    Hss32GPll_cfgPllBwThrd,
    Hss32GPll_cfgPllBwLow,
    Hss32GPll_cfgPllBwHigh,
    Hss32GPll_cfgPllCtlBufBypass,
    Hss32GPll_cfgPllShortLockEn,
    Hss32GPll_cfgRefClkSel,
    Hss32GPll_TOTALCNT
};

enum sys_tmg_serdes_comm_config_list_item_e
{
    Hss32GCom_cfgRefClkPllaDiv,
    Hss32GCom_cfgRefClkPllbDiv,
    Hss32GCom_cfgHssSramBootloadBypass,
    Hss32GCom_cfgRxTermOffset,
    Hss32GCom_cfgTxdnTermOffset,
    Hss32GCom_cfgTxupTermOffset,
    Hss32GCom_cfgSupMisc,
    Hss32GCom_cfgRxVrefCtrl,
    Hss32GCom_TOTALCNT
};

enum sys_tmg_serdes_tx_config_list_item_e
{
    Hss32GTxPerLane_cfgTxMisc,
    Hss32GTxPerLane_cfgTxDccCtrlDiffRange,
    Hss32GTxPerLane_cfgTxDccCtrlCmRange,
    Hss32GTxPerLane_cfgTxWidth,
    Hss32GTxPerLane_cfgTxRopllCpCtlIntg,
    Hss32GTxPerLane_cfgTxRopllCpCtlProp,
    Hss32GTxPerLane_cfgTxRopllRcFilter,
    Hss32GTxPerLane_cfgTxRopllV2iMode,
    Hss32GTxPerLane_cfgTxRopllVcoLowFreq,
    Hss32GTxPerLane_cfgTxRopllPostDiv,
    Hss32GTxPerLane_cfgTxRate,
    Hss32GTxPerLane_cfgTxTermCtrl,
    Hss32GTxPerLane_cfgTxDlyCalEn,
    Hss32GTxPerLane_cfgTxPllWordClkFreq,
    Hss32GTxPerLane_cfgTxDualCntxEn,
    Hss32GTxPerLane_cfgTxRopllBypass,
    Hss32GTxPerLane_cfgTxRopllRefDiv,
    Hss32GTxPerLane_cfgTxRopllRefSel,
    Hss32GTxPerLane_cfgTxRopllFbDiv,
    Hss32GTxPerLane_cfgTxRopllOutDiv,
    Hss32GTxPerLane_cfgTxRopllWordClkDivSel,
    Hss32GTxPerLane_cfgTxFastEdgeEn,
    Hss32GTxPerLane_cfgTxAlignWideXferEn,
    Hss32GTxPerLane_cfgTxPllEn,
    Hss32GTxPerLane_TOTALCNT
};

enum sys_tmg_serdes_rx_config_list_item_e
{
    Hss32GRxPerLane_cfgRxRefLoadValue,
    Hss32GRxPerLane_cfgRxVcoLoadValue,
    Hss32GRxPerLane_cfgRxCdrPpmMax,
    Hss32GRxPerLane_cfgRxEqAttLevel,
    Hss32GRxPerLane_cfgRxEqCtleBoost,
    Hss32GRxPerLane_cfgRxEqCtlePole,
    Hss32GRxPerLane_cfgRxEqAfeRate,
    Hss32GRxPerLane_cfgRxEqVgaGain,
    Hss32GRxPerLane_cfgRxEqAfeConfig,
    Hss32GRxPerLane_cfgRxEqDfeTap1,
    Hss32GRxPerLane_cfgRxEqDfeTap2,
    Hss32GRxPerLane_cfgRxDeltaIq,
    Hss32GRxPerLane_cfgRxCdrVcoConfig,
    Hss32GRxPerLane_cfgRxDccCtrlDiffRange,
    Hss32GRxPerLane_cfgRxDccCtrlCmRange,
    Hss32GRxPerLane_cfgRxSigdetLfThrd,
    Hss32GRxPerLane_cfgRxSigdetHfThrd,
    Hss32GRxPerLane_cfgRxMisc,
    Hss32GRxPerLane_cfgRxTermCtrl,
    Hss32GRxPerLane_cfgRxWidth,
    Hss32GRxPerLane_cfgRxRate,
    Hss32GRxPerLane_cfgRxDfeBypass,
    Hss32GRxPerLane_cfgRxOffcanCont,
    Hss32GRxPerLane_cfgRxAdaptCont,
    Hss32GRxPerLane_cfgRxEqDfeFloatEn,
    Hss32GRxPerLane_cfgRxCdrSscEn,
    Hss32GRxPerLane_cfgRxSigdetHfEn,
    Hss32GRxPerLane_cfgRxSigdetLfpsFilterEn,
    Hss32GRxPerLane_cfgRxTermAcdc,
    Hss32GRxPerLane_cfgRxAdaptSel,
    Hss32GRxPerLane_cfgRxAdaptMode,
    Hss32GRxPerLane_cfgRxAdaptEn,
    Hss32GRxPerLane_cfgRxTermEn,
    Hss32GRxPerLane_TOTALCNT
};

enum sys_tmg_serdes_speed 
{
    TMG_SERDES_SPEED_1_25G,
    TMG_SERDES_SPEED_3_125G,
    TMG_SERDES_SPEED_5G,
    TMG_SERDES_SPEED_5_15625G,
    TMG_SERDES_SPEED_10G,
    TMG_SERDES_SPEED_10_3125G,
    TMG_SERDES_SPEED_25_78125G,
    TMG_SERDES_SPEED_10_9375G,
    TMG_SERDES_SPEED_11_40625G,
    TMG_SERDES_SPEED_12_5G,
    TMG_SERDES_SPEED_12_96875G,
    TMG_SERDES_SPEED_27_78125G,
    TMG_SERDES_SPEED_27_34375G,
    TMG_SERDES_SPEED_28_125G,    
    TMG_SERDES_SPEED_TOTALCNT
};

#define TMG_TXFFE_PRE_MAX       24
#define TMG_TXFFE_MAIN_MAX      24
#define TMG_TXFFE_POST_MAX      32
#define TMG_TXFFE_FULL_SWING    96

/* Pattern selection */
typedef enum
{
    TMG_SERDES_PAT_DISABLE  = 0,
    TMG_SERDES_PAT_PRBS31   = 1,
    TMG_SERDES_PAT_PRBS23   = 2,
    TMG_SERDES_PAT_PRBS23_1 = 3,
    TMG_SERDES_PAT_PRBS16   = 4,
    TMG_SERDES_PAT_PRBS15   = 5,
    TMG_SERDES_PAT_PRBS11   = 6,
    TMG_SERDES_PAT_PRBS9    = 7,
    TMG_SERDES_PAT_PRBS7    = 8,
    TMG_SERDES_PAT_FIXED_PAT0 = 9,
    TMG_SERDES_PAT_DC_BALANCE = 10,
    TMG_SERDES_PAT_FIXED_PAT1 = 11,  /*(000, PAT0, 3ff, ~PAT0): 10-bit, 20-bit, and 40-bit TX width
                                      (00, PAT0, ff, ~PAT0): 8-bit, 16-bit, 32-bit TX width*/
    TMG_SERDES_PAT_EXTENDED   = 12,    
    TMG_SERDES_PAT_PRBS13     = 13
}sys_tmg_serdes_pattern_sel_e;

typedef struct sys_tmg_serdes_margin_param_s
{
    int16 margin_vdac;
    int8  margin_iq;
    uint8  clear;
    uint8  enable;

}sys_tmg_serdes_margin_param_t;

#define SYS_TMG_SERDES_MARGIN_VOLT_CNT     64
#define SYS_TMG_SERDES_MARGIN_PHASE_CNT    128

typedef enum sys_tmg_serdes_eye_e
{
    SYS_TMG_SERDES_EYE_WIDTH,
    SYS_TMG_SERDES_EYE_HEIGHT    
}sys_tmg_serdes_eye_t;

typedef struct sys_tmg_lt_status_s
{
    uint8 lt_start      : 1;   
    uint8 lt_complete   : 1;
    uint8 lt_done       : 1;
    uint8 lt_fail       : 1;
    uint8 lt_framelock  : 1;
    uint8 lt_progress   : 1;

}sys_tmg_lt_status_t;

typedef struct sys_tmg_serdes_pll_cfg
{
    uint16 multi        :12;
    uint16 tx_clk_div   :4; 
}sys_tmg_serdes_pll_cfg_t;

typedef enum
{
    RX_NO_SIGNAL,       /*sigdet = 0*/
    RX_VALID_SIGNAL,    /*sigdet = 1 && CDR lock*/
    RX_INVALID_SIGNAL,  /*sigdet = 1 && CDR unlock*/
}_sys_tmg_serdes_signal_valid_e;

typedef enum _sys_tmg_serdes_lt_fsm_state_e
{
    TMG_LT_FSM_INIT           = 0,
    TMG_LT_FSM_RXADAPT_INPROG = 1,
    TMG_LT_FSM_PHY_RXRST      = 2,
    TMG_LT_FSM_PHY_RXDATAEN   = 3,
    TMG_LT_FSM_SEND_TR        = 4,
    TMG_LT_FSM_TRAIN_LOCAL    = 5,
    TMG_LT_FSM_TRAIN_REMOTE   = 6,
    TMG_LT_FSM_LINK_RDY       = 7,
    TMG_LT_FSM_SEND_DATA      = 8,
    TMG_LT_FSM_TRAIN_FAIL     = 9,
    TMG_LT_FSM_MAX
}_sys_tmg_serdes_lt_fsm_state_t;

#endif

